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| single-chip 32-bit cmos micr ocomputer features ? cpu .......................................................... m32r family cpu core ? pipeline ............................................................ .................. 5 steps ? basic bus cycle ................................. 15 ns (at internal 66.6 mhz) ? logical address space ............................................ 4g-byte linear ? external bus ........................................................ data bus: 16 bits address bus: 24 bits ? internal dram ................................................. 8m bits (1m bytes) ? cache .......................................................... 4k bytes (direct map) ? register configuration ...... general-purpose registers: 32 bits x 16 control registers: 32 bits x 5 ? instruction set ....................... 83 instructions/6 addressing modes ? instruction format .................................................... 16 bits/32 bits ? multiply-accumulate operation unit (dsp function instruction ) ? internal memory controller ? programmable i/o ports ? power management function .................................. standby mode /cpu sleep mode ? pll clock generating circuit ................. four-time clock pll circuit ? operation mode .............................................. master/slave mode ? interrupt input ............................................................ ___ ___ int and sbi ? power source .......................................................... 3.3 v (10 %) applications portable equipment, still camera, navigation system, digital instrument, printer, scanner, fa equipment description the M32000D3FP is a new generation microcomputer with a 32-b it cpu and built-in high capacity dram. using this device it is possible to implement the complex applications of the multimedia age with high performance and low power consumption. the M32000D3FP contains 1m bytes of dram and 4k bytes of cac he memory. the cpu is implemented with a risc architecture and has a high performance figure of 52.4 mips (at an internal clock rate of 66.6 mhz ). memory for main storage is provided internally t o the device eliminating external memory and associated control ci rcuits thus reducing overall system noise and power consumption. the cpu, internal dram and cache memory are connected by a 128-bit, 15 ns/cycle internal bus which virtually eliminates transfer bottlenecks in between the cpu and the memory. the m32000d3f p internally multiplies the frequency of the input clock sign als by four. for an internal operating frequency of 66.6 mhz the input cl ock fre- quency is 16.65mhz. a 16-bit data and 24-bit address bus are the M32000D3FP's ex ter- nal bus and the interface to external peripheral controllers . when the hold state is set, the internal dram can be accessed from a n exter- nal device. a 3-chip basic system configuration using the M32000D3FP is the device itself plus an asic as a peripheral controller and a program rom. execution starts from the reset vector entry on the ext ernal rom after power on, a program requiring high speed execution is then transferred to internal dram and this is then executed . the M32000D3FP also has a slave mode additional to its master mo de. when set to slave mode the M32000D3FP can be used as a coprocessor. in this mode it does not access its external bu s immediatly after reset, but waits for the master to start it s operation. mitsubishi microcomputers M32000D3FP
single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 2 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 m3 20 00 d 3f p 100 -p in q f p /0 .6 5 m m pitch vc c a1 9 a1 8 a1 7 a1 6 vs s a1 5 a1 4 *1 vc c st b y dc bs pll v cc pl lv s s pl l c a p vs s cl ki n *2 pp 1 pp 0 cs a1 3 a1 2 vs s a1 1 a10 a9 a8 vc c vc c a3 0 a2 9 a2 8 a2 7 vs s a2 6 bc h bc l sid vc c r/ w *1 vc c vs s vs s vc c *1 *1 *1 rs t m/ s a2 5 a2 4 vs s a2 3 a22 a2 1 a2 0 vc c vs s d7 d6 d5 d4 vc c vc c vs s vs s vc c hreq *1 sb i in t hac k d3 d2 d1 d0 vs s vs s d1 5 d1 4 d1 3 d1 2 vc c b urs t st vc c vss vc c vss vc c wk u p vc c d1 1 d1 0 d9 d8 vs s note: connect *1 pins to vcc. connect *2 pins to vss. single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 3 block diagram m 3 2 0 00d3fp clki n dram (1 m b y t e s ) me mo r y cont rol l e r pll cl ock gen e r at i ng ci r c ui t 32 bi t s 32 bi t s pc alu shi f t m u lt ip ly - a ccu mu l a t e uni t 3 2 x 16 bi t s mul + 56- b i t - a c c regi st er 32 bi t s x 16 cach e m e m o r y (4 k b y te s ) i ns t r u c t io n qu eu e ( 128 bi t s x 2 st ag es ) dat a sel ect or 32 bi t s ? 128 bi t s i n st ruc t i on deco d er l oad / s t ore 128 12 8 128 128 12 8 m32r cpu c o re pp1 p r ogr am m abl e i / o por t pp0 a8 - a30 d0 - d15 bcl bs st r/ w burst dc hr e q hack cs si d ext ern a l bus i n t e r f ace uni t 128 bi t s ? 16 b i t s 23 m/ s rst sbi in t wk u p 128- bi t i nt er nal bus stby bch pllcap pllvcc pllvss 16 single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 4 functions function block characteristics cpu core ? bus specification basic bus cycle: 15 ns (internal operation at 66.6 mhz) logical address space: linear 4g bytes ____ ____ external address bus: 24 bits (external output pin: a8 to a3 0, bch, bcl) external data bus: 16 bits ? implementation: 5-stage pipeline ? core internal: 32 bits ? register configuration general-purpose registers: 32 bits 5 16 control registers: 32 bits 5 5 ? instruction set 16-bit/32-bit instruction format 83 instructions/6 addressing modes ? multiply-accumulate operation built in internal dram ? 8m bits (1m bytes) cache memory ? 4k bytes (internal instruction/data cache mode, instructio n cache mode, cache-off mode) memory controller ? cache control ? internal dram control, refresh control ? power management function (standby mode, cpu sleep mode se lection control) programmable i/o port ? two programmable i/o ports single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 5 pin function diagram clkin rst M32000D3FP clock system control vcc vss 16 15 a8 - a30 address bus 23 d0 - d15 data bus 16 hreq hack sid bus control bch bs dc bcl interrupt input pp0 pp1 st r/w burst cs m/s programmable i/o port sbi int wkup stby pllcap pllvcc pllvss single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 6 pin description (1/3) type pin name name i/o function power vcc power source C all power source pins should be connected to vcc. source vss ground C all ground pins should be connected to vss. clock clkin clock input input clock input pin. the M32000D3FP has an internal pll multipli er circuit, and an input clock which is 1/4 of the internal ope rating frequency (when the internal operating frequency is 66.6 mhz , the clkin input is 16.65 mhz). pllcap c connection C connects a capacitor for the internal pll. for pll pllvcc power source C power source for the internal pll. for pll pllvss ground C ground for the internal pll. for pll system ____ rst reset input internally resets the M32000D3FP. it is also used to return from control standby mode and cpu sleep mode. _ m/s master/slave input sets the M32000D3FP default operation to either system bus master (m/s = "h") or bus slave (m/s = "l"). when the M32000D3FP is set to bus slave, it does not carry o ut a reset vector entry fetch after a reset. _ the setting of m/s cannot be changed during operation. keep at either an "h" or an "l" level. ______ wkup wakeup input input pin to request return from standby mode. _____ this is only accepted when stby is "l" level. it generates the wakeup interrupt. _____ stby standby output indicates that the M32000D3FP has switched to standby mode. an "l" level is output while the device is in standby mode. address a 8 t o a 3 0 address bus i/o the M32000D3FP has a 24-bit address (a8 to a31) bus for a 16 mb b u s address space. a31 is not output. during the write cycle, th e ____ valid byte positions on the 16-bit data bus are output as bc h or ____ bcl. during the read cycle, the 16-bit data bus is read, how ever, only data in the valid byte positions is transferred to the M32000D3FP. address bus pins are bidirectional. when accessing the inter nal dram from an external bus master while the M32000D3FP is in the hold state, input the address from the system bus side. data bus d0 to d15 data bus i / o 16-bit data bus for connecting to external devices. (hi-z) * * (hi-z): this pin goes to high-impedance in the hold state. (hi-z)* single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 7 pin description (2/3) type pin name name i/o function bus sid space i/o space identifier between user space and i/o space. control identifier (hi-z)* sid = "l": user space sid = "h": i/o space sid is bidirectional. when accessing the internal dram from outside the M32000D3FP while the M32000D3FP is in the hold state, input an "l" level from the system bus side. ____ ____ bch, bcl byte control i/o indicates the valid byte positions of transferred data. (hi-z)* ____ ____ bch corresponds to the msb side (d0 to d7), and bcl correspo nds ____ to the lsb side (d8 to d15). during a read bus cycle, both b ch ____ and bcl are an "l" level. ____ ____ during a write bus cycle, either bch and/or bcl is an "l" l evel depending on the byte(s) to be written. when accessing the internal dram from an external bus master , the byte control signal is input from the system bus side. __ bs bus start output __ when the M32000D3FP drives an external bus cycle, bs goes to an "l" level at the start of the bus cycle. __ in burst transfer, bs goes to the "l" level for each transf er cycle. when accessing internal resources such as an internal __ dram or internal i/o register, bs is not output. st bus status output indicates whether the bus cycle that the M32000D3FP drives i s an instruction fetch access cycle or an operand access cycle . st = "l": for instruction fetch access st = "h": for operand access st = undefined: when idle __ r/w read/write i/o __ outputs r/w to identify whether the external bus cycle a rea d or a write cycle. when accessing the internal dram from an exte rnal __ bus master, r/w is input from the external bus. ______ burst burst output the M32000D3FP drives two consecutive bus cycles to access 32-bit data allocated on the 32-bit word boundary. for instruction fetches, it drives 8 (max.) consecutive cycl es (8 cycles in instruction cache mode) to data on the 128-bit boundary. ______ during these consecutive bus cycles, burst goes to "l" level . when accessing 32-bit data, an "l" level followed by an "h" level is output from address a30, because the msb-side 16 bits are accessed prior to the lsb-side 16 bits. when accessing 128-bit data, the addresses are output from a n arbitrary 16-bit aligned address and wraparound within a 128 -bit aligned boundary. * (hi-z): this pin goes to high-impedance in the hold state. (hi-z)* (hi-z)* (hi-z)* (hi-z)* single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 8 type pin name name i/o function bus __ dc* data complete i/o when the M32000D3FP drives an external bus cycle, it control __ automatically inserts wait cycles until dc is input by the s lave (cont.) device in the system bus. when the M32000D3FP is in the hold state and the internal dram is accessed from an external bus master, the M32000D3FP __ outputs dc to notify to the external bus master that the bus cycle to the internal dram has been completed. ______ hreq hold input ______ bus right request input pin of the system bus. when hreq is an "l" level, the M32000D3FP switches to the hold state. _____ hack hold output indicates that the M32000D3FP has switched to the hold state acknowledge and releases the bus right of the system bus to the requesto r. __ cs chip input signal input to the M32000D3FP when it is in the hold state to select request access to the internal dram from an external bus mas ter. __ when an "l" level is input to cs, the M32000D3FP accesses the internal dram at the address input via the address pins. interrupt ___ sbi system input ___ system break interrupt input pin. the sbi is not masked by t he controller break i e bit in the psw register. it is also used to return from cpu interrupt sleep mode and to request the start of operation in slave mo de. ___ int external input external interrupt request input pin. it is also used to ret urn from interrupt cpu sleep mode and to request the start of operation the sla ve mode. programm- pp0, pp1 port i/o two programmable i/o ports. able i/o port __ __ * the dc pin becomes an output pin when the cs signal is inp ut to the M32000D3FP. pin description (3/3) (hi-z) single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 9 functional description cpu the m32r cpu has 16 general-purpose registers, 5 control reg is- ters, an accumulator and a program counter. the accumulator is of 64-bit width. the registers and program counter are of 32-bi t width. general-purpose registers the 16 general-purpose registers (r0 - r15) are of 32-bit wi dth and are used to retain data and base addresses. r14 is used as t he link register and r15 as the stack pointer (spi or spu). the link register is used to store the return address when executing a subrout ine call instruction. the interrupt stack pointer (spi) and the user stack pointer (spu) are alternatively represented by r15 depending on the value of the stack mode bit (sm) in the processor status word regi ster (psw). control registers there are 5 control registers which are the processor status word register (psw), the condition bit register (cbr), the interr upt stack pointer (spi), the user stack pointer (spu) and the backup p c (bpc). the mvtc and mvfc instructions are used for writing and reading these control registers. r0 r1 r2 r3 r4 r5 r6 r7 31 0 r8 r9 r10 r11 r12 r13 r14 (link register) r15 (stack pointer) 31 0 (see note) note: the interrupt stack pointer (spi) and the user stack pointe r (spu) are alternatively represented by r15 depending on the value of t he stack mode bit (sm) in the psw. fig. 1 general-purpose registers processor status word register condition bit register interrupt stack pointer user stack pointer backup pc 31 0 cr0 cr1 cr2 cr3 cr6 (see notes) crn notes 1: crn (n = 0 - 3, 6) denotes the control register number. 2: the mvtc and mvfc instructions are used for writing and reading these control registers. psw cbr spi spu bpc fig. 2 control registers single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 10 processor status word register: psw (cr0) the processor status word register (psw) shows the m32r cpu status. it consists of the current psw field, and the bpsw f ield where a copy of the psw field is saved when eit occurs. the psw field is made up of the stack mode bit (sm), the int errupt enable bit (ie) and the condition bit (c). the bpsw field is made up of the backup stack mode bit (bsm), the backup interrupt ena ble bit (bie) and the backup condition bit (bc). note: "init." ...initial state immediately after reset " r " .... : read enabled " w " .... : write enabled d bit name function init. r w 16 bsm (backup sm) saves value of sm bit when eit occurs undefined 17 bie (backup ie) saves value of ie bit when eit occurs undefined 23 bc (backup c) saves value of c bit when eit occurs undefined 24 sm (stack mode) 0: uses r15 as the interrupt stack pointer 0 1: uses r15 as the user stack pointer 25 ie (interrupt enable) 0: does not accept interrupt 0 1: accepts interrupt 31 c (condition bit) indicates carry, borrow and overflow resulting 0 from operations (instruction dependent) fig. 3 processor status word register 16 17 23 24 25 31 15 8 7 0 sm ie c bc bsm bie 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 psw bpsw field psw field single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 11 condition bit register the condition bit register (cbr) is a separate read-only reg ister which contains a copy of the current the condition bit (c) in the psw. this register is read-only. an attempt to write to the cbr with t he mvtc instruction is ignored. interrupt stack pointer, user stack pointer the interrupt stack pointer (spi) and the user stack pointer (spu) retain the current stack address. the spi and spu can be acc essed as the general-purpose register r15. r15 switches between re pre- senting the spi and spu depending on the value of the stack mode bit (sm) in the psw. backup pc the backup pc (bpc) is the register where a copy of the pc v alue is saved when eit occurs. bit 31 is fixed at "0". when eit occ urs, the pc value immediately before eit occurrence or that of the ne xt in- struction is set. the value of the bpc is reloaded to the pc when the rte instruction is executed. however, the values of the lower 2 bits of the pc become "00" on returning (it always returns to the word boundary). 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cbr c 0 0 0 0 0 31 0 bpc bpc 0 fig. 4 condition bit register, interrupt stack pointer, use r stack pointer and backup pc 31 0 spi spu spu 31 0 spi single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 12 accumulator the accumulator (acc) is a 64-bit register used for dsp type func- tions. use the mvtachi and mvtaclo instructions for writing to the accumulator. the high-order 32 bits (bit 0 - bit 31) can be set with the mvtachi instruction and the low-order 32 bits (bit 32 - bit 63) can be set with the mvtaclo instruction. use the mvfachi , mvfaclo and mvfacmi instructions for reading from the accumu- lator. the high-order 32 bits (bit 0 - bit 31) are read with the mvfachi instruction, the low order 32 bits (bit 32 - bit 63) with th e mvfaclo instruction and the middle 32 bits (bit 16 - bit 47) with th e mvfacmi instruction. program counter the program counter (pc) is a 32-bit counter that retains th e ad- dress of the instruction being executed. since the m32r cpu in- struction starts with even-numbered addresses, the lsb (bit 31) is always "0". fig. 5 accumulator 31 0 pc pc 0 fig. 6 program counter 32 48 63 31 16 15 0 47 78 acc (see note) read/write range with mvtaclo or mvfaclo instruction read/write range with mvtachi or mvfachi instruction read range with mvfacmi instruction note: bits 0 - 7 are always read as the sign-extended value of bit 8. an attempt to write to this area is ignored. single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 13 data types signed and unsigned integers of byte (8 bits), halfword (16 bits), and word (32 bits) types are supported as data in the m32r cpu i nstruc- tion set. a signed integer is represented in a 2's complemen t format. data formats data size of a register of the m32r cpu is always a word (32 bits). byte (8 bits) and halfword (16 bits) data in memory are sign -extended (the ldb and ldh instructions) or zero-extended (the ldub and lduh instructions) to 32 bits, and loaded into the register. word (32 bits) data in a register is stored to memory by the st in- struction. halfword (16 bits) data in the lsb side of a regi ster is stored to memory by the sth instruction. byte (8 bits) data in the lsb side of a register is stored to memory by the stb instruction. data stored in memory can be one of these types: byte (8 bit s), halfword (16 bits) or word (32 bits). although the byte data can be located at any address, the ha lfword data and the word data can only be located on the halfword b ound- ary and the word boundary, respectively. if an attempt is ma de to access data in memory which is not located on the correct bo undary, an address exception occurs. signed byte (8-bit) integer unsigned byte (8-bit) integer signed halfword (16-bit) integer 0 0 0 0 0 0 7 7 15 15 31 31 s s s s: sign bit unsigned halfword (16-bit) integer signed word (32-bit) integer unsigned word (32-bit) integer rn 0 31 < load > byte rn 0 31 halfword rn 0 31 word sign-extention ( ldb instruction) or zero-extention ( ldub instruction) from memory ( ldb , ldub instruction) < store > rn 0 31 byte rn 0 31 halfword rn 0 31 word to memory ( stb instruction) to memory ( sth instruction) to memory ( st instruction) from memory ( ldh , lduh instruction) from memory ( ld instruction) 24 16 24 16 sign-extention ( ldh instruction) or zero-extention ( lduh instruction) fig. 7 data type fig. 8 data format address byte halfword word + 0 + 1 + 2 + 3 byte byte byte byte halfword halfword word 7 8 31 16 15 15 8 7 0 16 23 24 single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 14 address space the M32000D3FP logical address is 32-bit wide and offers 4 g b linear space. the M32000D3FP has address spaces allocated as shown below. the user space is specified by sid = 0 (h'0000 0000 to h'7ff f ffff). the area available to the user is 16 mb from address h'0000 0000 to address h'00ff ffff. the i/o space is specified by sid = 1 (h'8000 0000 to h'ffff ffff). the area available to the user is 16 mb from address hff00 0000 to address h'ffff ffff. the i/o space cannot be cached. these areas below are allocated in each space. ? user space internal dram area external area ? i/o space user i/o area system area internal i/o area fig. 9 address space h'0000 0000 h'ffff ffff < logical space > eit vector entry (reset interrupt) h'7fff ffff h'8000 0000 i/o space (sid = 1) user space (sid = 0) < physical space > internal dram area (1m bytes) h'0000 0000 h'000f ffff h'0010 0000 h'00ff ffff external area (15m bytes) logical address 0 : h'00 0000 0 : h'0f ffff 0 : h'10 0000 0 : h'ff ffff (16m bytes) (16m bytes) h'ff00 0000 h'ff7f ffff h'ff80 0000 h'ffff ffff h'ffbf ffff h'ffc0 0000 1 : h'00 0000 1 : h'bf ffff 1 : h'ff ffff 1 : h'c0 0000 1 : h'7f ffff 1 : h'80 0000 user i/o area (8m bytes) system area (4m bytes) internal i/o area (4m bytes) physical address (24 bits) eit vector entry (except for reset interrupt) sid physical address (24 bits) sid logical address logical address single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 15 the user i/o area is 8 mb from address h'ff00 0000 to addres s h'ff7f ffff. when this space is accessed, the control signal s to access external devices are output. the system area is 4 mb from address h'ff80 0000 to address h'ffbf ffff. this area is res erved for development tools such as in-circuit emulators or debug moni- tors. the user cannot use this area. the internal i/o area is 4 mb from address h'ffc0 0000 to ad dress h'ffff ffff. the memory controller and programmable i/o port registers are allocated in this area. the internal dram (1 mb) is allocated from address h'0000 00 00 to address h'000f ffff. the eit vector entry (other than the re set interrupt) is allocated in the address h'0000 0000 to addres s h'0000 008f of this area. the internal dram is connected to the m32r cpu via a 4 kb ca che memory with a 128-bit bus. when the M32000D3FP is in the hol d state, the internal dram can be accessed from an external bu s master by inputting control signals. the external area consists of 15 mb from address h'0010 0000 to address h'00ff ffff. when this space is accessed, the contro l sig- nals to access external devices are output. the bottom 16 by tes in this area (h'00ff fff0 to h'00ff ffff) are the reset interru pt eit vector entry. fig. 10 internal i/o space memory map h'ffc0 0000 h'ffff ffe0 h'ffff ffe4 h'ffff ffe8 h'ffff fff8 h'ffff fffc logical address 0 31 +3 address (reserved) +2 address +1 address +0 address ppcr1 ppdr0 memory controller ppdr1 (reserved) mpmr mccr ppcr0 h'ffff ffec mlcr: lock control register mpmr: power management control register mccr: cache control register programmable i/o port ppcr0: programmable i/o port direction control register 0 ppcr1: programmable i/o port direction control register 1 ppdr0: programmable port data register 0 ppdr1: programmable port data register 1 mlcr h'ffff fff4 single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 16 eit events are shown below. ? reserved instruction exception (rie) the reserved instruction exception (rie) occurs when executi on of a reserved instruction (unimplemented instruction) is detected . ? address exception (ae) the address exception (ae) occurs if an attempt is made to a ccess an unaligned address with either a load instruction or a sto re instruc- tion. ? reset interrupt (ri) ___ the reset interrupt (ri) is always accepted when the rst sig nal is input. it has the highest priority. ? wakeup interrupt (wi) ______ the wakeup interrupt (wi) is accepted when the wkup signal i s input while the M32000D3FP is in standby mode. it is only us ed to return from standby mode. ? system break interrupt (sbi) ___ the system break interrupt (sbi) is an interrupt request fro m the sbi pin. it is used when a break in power source or an error fro m an external watchdog timer is detected. it is also used to retu rn from cpu sleep mode and to start an M32000D3FP set to slave mode. ? external interrupt (ei) ___ the external interrupt (ei) is an interrupt request from the int pin. it is used by an interrupt from the external peripheral i/o and can be masked by the ie bit in the psw register. it is also used to return from cpu sleep mode and to start an M32000D3FP set to slave mode. ? trap the trap (trap) is a software interrupt which is generated b y ex- ecuting the trap instruction. a total of 16 eit vector entri es are available for operands 0 to 15 of the trap instruction. fig. 11 eit events eit exception reserved instruction exception (rie) address exception (ae) interrupt reset interrupt (ri) wakeup interrupt (wi) system break interrupt (sbi) trap trap (trap) external interrupt (ei) eit while the cpu is executing a program, sometimes it is necess ary to suspend execution, because a certain event occurs, and execu te another program. these kinds of events are referred to as ei t (ex- ception, interrupt, trap). ? exception the event is related to the context being executed. it is ge nerated by errors or violations that occur during instruction execution . with the M32000D3FP, the address exception (ae) and reserved instruct ion exception (rie) are of this type. ? interrupt the event is not related to the context being executed. it i s gener- ated by an external hardware signal. with the M32000D3FP, th e external interrupt (ei), system break interrupt (sbi), wakeu p inter- rupt (wi) and reset interrupt (ri) are of this type. ? trap this is a software interrupt which is generated by executing the trap instruction. it is intentionally added to the program by the program- mer, as a system call. single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 17 internal memory system the memory system built into the M32000D3FP has the followin g characteristics. ? internal 8m-bit (1m-byte) dram ? internal 4k-byte cache memory ? cpu, cache and internal dram are connected by a 128-bit bu s ? selectable cache memory operation mode C internal instruction/data cache mode C instruction cache mode C cache-off mode when the internal instruction/data cache mode is selected, t he cache memory functions as a cache for both instruction and data fr om the internal dram, and caches all bus access to the dram. this m ode is for a system which uses the internal dram as main memory. trans- fer between the m32r cpu, cache memory and internal dram is always carried out in blocks of 128 bits. caching is carried out by the direct map method. writing is by the copy back method. when the M32000D3FP access destination is an external space, data transfer between the m32r cpu and the external device i s car- ried out via the bus interface unit (biu). the biu has a 128 -bit data buffer which converts the bus width between the 128-bit bus in the M32000D3FP and the external bus. caching is not applicable i n this case of data transfer. when accessing the internal dram from an external bus master , and a cache hit occurs (the accessed data is inside the cach e), data transfer between the cache memory and the external bus via t he biu is carried out. when a cache miss occurs, (the accessed data is not inside the cache) data transfer is carried out between the i nternal dram and the external bus via the biu without cache replacem ent. cache control register (mccr) < address: h'ffff ffff> d24 d25 d26 d27 d28 d29 d30 d31 cp cm0 cm1 single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 18 when the instruction cache mode is selected, the cache funct ions as an instruction cache for the internal dram or the external m emory, and caching is carried out for instruction fetch access. thi s mode is designed for use when an external rom is used as program mem ory and the internal dram is used as data memory, or when instru ctions are located in the internal dram. caching is carried out by the direct map method. when instruction codes in the user space are ove rwrit- ten by the external bus master or another source, instructio n code coherency in the cache memory is not guaranteed. furthermore , caching is not applied when accessing the internal dram from the external bus master. when the cache-off mode is selected, the M32000D3FP internal memory system is configured as follows. in this mode, cachin g is not applied, and all bus cycles are directly to the internal dra m or exter- nal bus. external bus (16 bits) 16 external bus interface M32000D3FP 128 instruction cache biu 128 dram cpu 128 external bus (16 bits) 16 external bus interface M32000D3FP 128 dram biu cpu fig. 14 instruction cache mode fig. 15 cache-off mode single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 19 bus interface unit (biu) the M32000D3FP has the following signals related to the exte rnal bus. ? address (a8 to a30) the M32000D3FP has a 24-bit address bus (a8 to a31) correspo nd- ing to a 16 mb address space. of these, a31 (the lsb) is not output externally. in write cycles, the validity of the two bytes o utput on the ___ ___ 16-bit data bus is indicated by bch and/or bcl. in read cyc les, the 16-bit data bus is always read, however, only data in the va lid byte position in the M32000D3FP is transferred. the address pins are bidirectional. if the M32000D3FP is in the hold state and th e internal dram is accessed from an external bus master, the address si gnal is input from the system bus side. ? space identifier (sid) the space identifier is used to specify user space and i/o s pace. user space: sid = "l" i/o space: sid = "h" if the M32000D3FP is in the hold state and the internal dram is accessed from an external bus master, the "l" level should b e input to sid from the system bus side. ___ ___ ? byte control (bch, bcl) byte control signals indicate the byte position of valid dat a trans- ___ ferred of the external bus cycle. bch corresponds to the msb side ________ (d0 to d7), and bcl corresponds to the lsb side (d8 to d15). dur- ___ ___ ing the bus read cycle, both bch and bcl are an "l" level. d uring ___ ___ the bus write cycle, bch and/or bcl go to an "l" level depen ding on the bytes to be written. if the M32000D3FP is in the hold st ate and the internal dram is accessed from an external bus master, t he byte control signal is input from the system bus side. ? data bus (d0 to d15) the M32000D3FP has a 16-bit data bus to access external devi ces. if the M32000D3FP is in the hold state and the internal dram is accessed from an external bus master, the data bus is used a s a data i/o bus from the system bus side. __ ? bus start (bs) when the M32000D3FP drives the bus cycle to the system bus, an __ "l" level is output to bs at the start of the bus cycle. als o, for a burst __ __ transfer, the bs signal is output for each transfer cycle. t he bs sig- nal is not output when accessing internal resources such as the in- ternal dram or internal i/o registers. ? bus status (st) the st signal identifies whether the bus cycle the m32000d3f p is driving is an instruction fetch cycle or an operand access c ycle. instruction fetch access: st = "l" operand access: st = "h" hold: st = high-impedance idle: st = undefined __ ? read/write (r/w) __ the M32000D3FP outputs a r/w signal to identify whether the ex- ternal bus cycle is a read or write operation. when accessin g the __ internal dram from an external bus master, a r/w signal is i nput from the system bus side. __ read bus cycle: r/w = "h" __ write bus cycle: r/w = "l" ______ ? burst (burst) the M32000D3FP drives two consecutive bus cycles to access 3 2- bit data located on the 32-bit boundary. in instruction fetc hing, it drives a maximum of 8 (fixed to 8 cycles in instruction cache mode) con- secutive read cycles to access data located on the 128-bit b oundary. while driving these consecutive bus cycles, the M32000D3FP o ut- ______ puts "l" level to burst. when accessing 32-bit data, the add ress of the msb-side 16 bits are output before the address of the ls b side 16 bits. when accessing 128-bit data, the addresses are outp ut for every access cycle from the arbitrary 16-bit aligned address es to wraparound within the 128-bit boundary. __ ? data complete (dc) when starting an external bus cycle, the M32000D3FP automati - __ cally inserts wait cycles until the dc signal is input from external. __ wait control using the dc signal is effective also for bus c ycles dur- ing burst transfer. when the M32000D3FP is in the hold state and if __ __ the cs signal is input, the M32000D3FP outputs the dc signal to notify the external bus master that internal dram access is com- plete. _____ _____ ? hold control (hreq, hack) the hold state is the state when the external bus access sto ps and all pins go to a high-impedance state. however, the internal dram can be accessed while the external bus is in the hold state. to put _____ the M32000D3FP into the hold state, input an "l" level to hr eq. when the hold request is accepted and the M32000D3FP enters the _____ hold state, an "l" level is output from hack. single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 20 read and write operations of the M32000D3FP are carried out using ___ _______ _______ _____ the address bus, data bus, and the r/w, bch, bcl and dc signals. ___ _______ when reading, the r/w signal goes to an "h" level, and the b ch and _______ bcl signals go to an "l" level. the cpu reads the data in th e valid ___ byte positions. when writing, an "l" level is output from r/ w, and _______ _______ bch and bcl are output according to the valid byte positions , so as to specify the byte positions for writing into an external d evice. keep dc signal at the "h" level during idle cycles. idle read "h" "h" clkin bs a8 - a30 sid, st bch, bcl burst d0 - d15 dc r/w idle read idle write idle write clkin bs a8 - a30 sid, st bch, bcl burst d0 - d15 dc r/w "h" "hi-z" "hi-z" "hi-z" "hi-z" note: "hi-z" means high-impedance, and indicates sampling ti ming. fig. 16 read/write timing (two no-wait accesses) __ ? internal dram access control (cs) __ the internal dram can be accessed when cs is driven to an "l " ____ level after the M32000D3FP enters the hold state (hack = "l" ). to access the internal dram from external, the following sig nals from the system bus side should be controlled. ? a8 to a30 input internal dram addresses to be read or written. ___ ___ ? bch, bcl specify the byte position of data to be written into the int ernal ___ ___ dram. bch corresponds to the msb side (d0 to d7), and bcl corresponds to the lsb side (d8 to d15). __ ? r/w ___ specify read or write operation. when reading, r/w = "h". wh en __ writing, r/w = "l". ? d0 to d15 16-bit data i/o bus. ? sid when accessing the internal dram from an external bus mas- ter, an "l" level is input to sid to specify user space. _____ ? dc this signal notifies to an external bus master that the inte rnal dram access is complete. when access is complete, an "l" _____ level is output to dc. table 1 pin condition in hold state pin name pin condition or operation a8 - a30, sid, high-impedance ____ ____ bch, bcl __ ___ ______ st, r/ w , bs, burst d 0 - d 1 5 output when internal dram is read __ by an external bus master (cs = "l", __ r/ w = "h"), otherwise high-impedance __ d c output when internal dram is accessed by an external bus master __ (cs = "l"), otherwise high-impedance _____ hack output "l" other pins normal operation single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 21 __ when an "l" level is input to dc, the next bus cycle is proc essed and __ wait cycles are inserted until this point. keep the dc signa l at the "h" level, unless otherwise necessary. when a write cycle comes imme- diately after a read cycle, the M32000D3FP inserts an idle c ycle to prevent a collision with data on the system bus. the same ap plies to write cycles (burst write access) immediately after a burst read cycle. fig. 17 read/write timing (two one-wait accesses) fig. 18 automatic idle cycle insertion between consecutive read and write cycles "h" "h" idle read clkin bs a8 - a30 sid, st bch, bcl burst d0 - d15 dc r/w idle read "h" idle write idle write clkin bs a8 - a30 sid, st bch, bcl burst d0 - d15 dc r/w "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" note: "hi-z" means high-impedance, and indicates sampling timing. keep dc signal at the "h" level during idle cycles. "h" idle clkin bs a8 - a30 sid, st bch, bcl burst d0 - d15 dc r/w idle read write idle "hi-z" "hi-z" "hi-z" note: "hi-z" means high-impedance, and indicates sampling t iming. keep dc signal at the "h" level during idle cycles. single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 22 ______ the M32000D3FP outputs the burst signal and carries out a bu rst transfer when reading "the word-size data aligned on the 32- bit bound- ary" or "a maximum 4 words of instructions aligned on the 12 8-bit ______ boundary". the burst signal is synchronized with the clkin f alling edge of the first bus access cycle and output "l" level. it returns to an "h" level synchronized with the first clkin falling edge of the last bus access cycle. addresses a8 to a30 are output for each cy cle. when burst reading 32-bit data, the msb-side 16-bit read bus cycle is carried out first followed by the lsb-side 16-bit read bu s cycle. when the cache memory operation mode is the instruction cach e mode, and burst reading of the instructions within the 128-b it bound- ary for cache replacement occurs, the bus cycle is driven a fixed 8 times from an arbitrary 32-bit boundary address and to wrapa round within the 128-bit boundary. when other than the instruction cache mode is selected and burst reading a set of instructions of less than 128 bits, consecutive bus cycles are driven from an arbitrar y 32-bit boundary address as the top to the 128-bit line (a28 to a30 = "111"). fig. 20 4-word (128-bit) burst read timing (1-0-0-0-0-0-0-0 wait) fig. 19 1-word (32-bit) burst read timing (1-0 wait) "h" idle clkin bs a8 - a30 sid, st bch, bcl burst d0 - d15 dc r/w burst read (1 word) idle "hi-z" "hi-z" note: "hi-z" means high-impedance, and indicates sampling ti ming. wait cycles can be inserted even when burst transferring by setting dc = "h". keep dc signal at the "h" level during idle cycles. wait cycles can be inserted even when burst transferring by setting dc = "h". "h" idle clkin bs a8 - a30 sid, st bch, bcl burst d0 - d15 dc r/w burst read ( 4 words) idle "hi-z" note: "hi-z" means high-impedance, and indicates sampling ti ming. keep dc signal to at the "h" level during idle cycles. single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 23 when writing word-size data aligned on the 32-bit boundary, the ______ M32000D3FP carries out a burst-transfer by outputting the bu rst signal. when burst-writing 32-bit data, the msb-side 16-bit write bus cycle is driven first, followed by the lsb-side 16-bit write bus cycle. ______ the burst signal is synchronized with the clkin falling edge of the first bus access cycle, and "l" level is output. it retu rns to "h" level in synchronization with the clkin falling edge of the last bus access cycle. addresses a8 to a30 are output for each cycle. _____ when an "l" level is input to hreq, the M32000D3FP switches to _____ the hold state and outputs an "l" level to hack. while the M32000D3FP is in the hold state, bus related pins go to a hi gh im- pedance state, and data transfer is carried out on the syste m bus. to _____ return to normal operation mode from the hold state, the hre q sig- nal should be changed to an "h" level. fig. 21 1-word (32-bit) burst write timing (1-0 wait) fig. 22 bus arbitration timing idle clkin bs a8 - a30 sid,st bch, bcl burst d0 - d15 dc r/w burst write (1 word) idle "hi-z" "hi-z" note: "hi-z" means high-impedance, and indicates sampling t iming. wait cycles can be inserted even when burst transferring by setting dc = "h". keep dc signal at the "h" level during idle cycles. "hi-z" "hi-z" "hi-z" (see note 2) "hi-z" "hi-z" "hi-z" "hi-z" notes 1: before switching to the hold state, an idle cycle of 1 clkin clock period is always inserted. after returning from the hold state, an idle cycle of 1 to 5 clkin clock periods is always inserted. 2: "hi-z" means high impedance, and indicates sampling timing. 3: while the M32000D3FP is in the hold state, the dc signal is driven and output when the cs signal is input. (see note 2) (see note 3) write clkin hreq bch, bcl d0 - d15 dc r/w idle hold shift hold return idle hack a8 - a30 sid, st (see note 1) (see note 1) bs burst single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 24 ("l" output) ("l" input) "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" ] hreq bch, bcl d0 - d15 dc r/w hold shift hold return hack a8 - a30 cs read read read read sid note: "hi-z" means high impedance, and indicates sampling timing. clkin the value of the r/w signal that controls the data direction of the bus interface cannot be changed during cs="l". hold this value while cs="l ". also, where marked above with ] , 3 to 7 clkin clock periods are necessary for the first read operation (also when reading crosses an 128-b it boundary) when reading from the internal dram. hold the input value of the address or other control signals during these wait cycle periods (dc = "h"). consecut ive read operations within an 128-bit boundary are completed in 1 clkin clock pe riod. during these wait cycle period, cs cannot be returned to an "h" level (the access cannot be aborted). cs can only be returned to an "h" level after dc is driven to "l". when the M32000D3FP is in the hold state and an "l" level is input __ to cs, the M32000D3FP interprets it as a bus access request to the __ internal dram. in this case, when the r/w signal is an "h" l evel, the memory controller drives a read cycle to the internal dram. in the read cycle, the 16-bit data for the address specified with a 8 to a30, ____ ___ is output from d0 to d15 regardless of the bch and bcl setti ngs. __ also the dc signal is output. the M32000D3FP reads 128 bits of data from the block on the 128- bit boundary including the requested address into the 128-bi t buffer of the bus interface unit. 3 to 7 clkin clock periods are ne cessary for the first bus access, however, when reading consecutive address within the 128-bit boundary, the subsequent read bus cycles are com- pleted in 1 clkin clock period because a read from the inter nal dram __ does not take place. after dc outputs an "l" level (access c omplete), __ return cs to the "h" level between the clkin falling edge co rre- sponding to the last read cycle and the following clkin fall ing edge. ______ return hreq to the "h" level to return the M32000D3FP to the nor- mal operation mode from the hold state either at the same ti me as or __ after cs is returned to the "h" level. fig. 23 read bus cycle to internal dram single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 25 ("l" output) ("l" output) ("l" output) "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" ] clkin hreq bch, bcl d0 - d15 dc r/w hold shift hold return hack a8 - a30 cs write write write write sid note: "hi-z" means high impedance, and indicates sampling t iming. the value of the r/w signal that controls the data direction of the bus interface cannot be changed during cs="l". hold this value while cs="l ". also, where marked above with ] , 3 to 7 clkin clock periods are necessary for writing operation to internal dram crossing an 128-bit boundary. hol d the input value of the address or other control signals during these wait cycle per iods (dc = "h"). consecutive writing operations within an 128-bit boundary are completed in 1 clkin clock period. during these wait cycle period, cs cannot be returned to "h" level (the access cannot be aborted). cs can only be returned to a "h" level a fter dc is driven to "l". when the M32000D3FP is in the hold state and an "l" level is input __ to cs, the M32000D3FP interprets it as a bus access request to the __ internal dram. in this case, when the r/w signal is at an "l " level, the memory controller drives a write cycle to the internal d ram. byte ____ ___ data control is specified by the bch and bcl signals. only d ata in ____ ___ the byte positions for which an "l" level is input to bch or bcl are __ written. when writing is complete, an "l" level dc signal is output. the M32000D3FP stores the requested data in the 128-bit data buffer of the biu, before writing to the internal dram. this reduce s the number of accesses to the internal dram when a request to wr iting to consecutive addresses is made, and improves bus cycle thr ough- put. consecutive write cycles within an 128-bit boundary are com- pleted in 1 clkin clock period. 3 to 7 clkin clock periods a re nec- essary for a write access crossing an 128-bit boundary when writing __ to the internal dram. after dc outputs an "l" level (access com- __ plete), return cs to the "h" level between the clkin falling edge corresponding to the last write cycle and the following clki n falling ______ edge. return hreq to the "h" level to return the M32000D3FP to the normal operation mode from the hold state either at the same __ time as or after cs is returned to the "h" level. when the external bus master makes an access, the value of t he __ r /w signal that controls the data direction of the bus interface can- __ not be changed during cs="l". therefore, read cycles and wri te cycles __ cannot be mixed while cs = "l". when starting a write cycle follow- ing after a read cycle and starting a read cycle following a write cycle, __ keep the cs signal at an "h" level for at least 1 clkin. fig. 24 write bus cycle to internal dram fig. 25 read/write bus cycle clkin hreq bch, bcl d0 - d15 dc r/w hold shift hold return hack a8 - a30 cs ("l" output) read cs = "h" write ("l" output) sid ("l" input) "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" ] "hi-z" "hi-z" note: "hi-z" means high-impedance, and indicates sampling t iming. also, where marked above with ] , keep cs signal to "h" at least 1 clkin when starting a write bus cycle after a read bus cycle or a read bus cycle after a write bus cycle. "hi-z" single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 26 master/slave mode _ the M32000D3FP has an m/s (master/slave) pin for multiproces sor configuration use. _ ? master mode (m/s = "h") _ this is normal operation mode. set the m/s pin to an "h" lev el. it is used when the M32000D3FP is used as the main cpu in a system . _ ? slave mode (m/s = "l") this operation mode is for when the M32000D3FP is used as a _ coprocessor. set the m/s pin to an "l" level. when set to sl ave mode, the M32000D3FP does not start operation even after a reset, until an interrupt request or the sbi is input. processing is carried out by communicating with the master M32000D3FP, using the two pro- grammable i/o ports and the external interrupt signal. ? coprocessor only configuration example the slave M32000D3FP accesses only the internal dram and nev er _ _____ the external bus. m/s and hreq are fixed at the "l" level. t he slave M32000D3FP executes the instructions that the master m32000d 3fp downloads to the internal dram. the data transfer request (p rocess- ing complete) from the slave M32000D3FP is notified to the m aster M32000D3FP by inputting the interrupt request via the progra mmable i/o port. the data transaction is carried out when the maste r M32000D3FP accesses the internal dram in the slave m32000d3f p. ? common bus coprocessor configuration example in this configuration, the slave M32000D3FP can also access the external bus. communications between the master and slave cp us is carried out using the programmable i/o ports and the inte rrupt request input. d24 d25 d26 d27 d28 d29 d30 d31 lm loc k control register (mlcr) < address: h'ffff fff7> fig. 26 lock control register M32000D3FP (master) rom asic pp0 m/s m/s hreq int M32000D3FP (slave) hack hreq hack bus arbiter int M32000D3FP (master) rom asic int pp0 m/s m/s hreq int M32000D3FP (slave) no access to external bus single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 27 in standby mode, all clock supply stops and only the content s of the internal dram are retained. the power requirement is only th at which the internal dram needs for refreshing itself. when set to s tandby mode, the M32000D3FP waits for the current bus operation to be completed. it then purges the cache memory and switches the inter- nal dram to self-refresh mode. after that, the pll and all c lock sup- _____ plies stop and the stby signal goes to an "l" level to indic ate the _____ completion of the switch to standby mode. input an "l" level to wkup ___ or rst to return from standby mode to normal operation mode. the contents of the internal dram are retained upon return using the _____ wkup signal. in cpu sleep mode, clock supply to the m32r cpu stops. in th is mode, the internal dram, cache memory, memory controller and external bus interface continue to operate and the internal dram ___ ___ can be accessed from the external bus. input an "l" level to int, sbi ___ or rst to return to normal operation mode from cpu sleep mod e. the contents of the cache memory, internal dram, general-pur pose registers and programmable i/o control register are retained upon ___ ___ return using the int or sbi signals. power management function the M32000D3FP has the following two low-power consumption modes. ? standby mode ? cpu sleep mode power management (mpmr) < address: h'ffff fffb> d24 d25 d26 d27 d28 d29 d31 pm1 pm0 d30 single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 28 programmable i/o port the M32000D3FP has two programmable i/o ports (pp0, pp1). ea ch port can be set as input or output. reset ____ when an "l" level is input to rst, the M32000D3FP switches t o the reset state. the reset state is released when an "h" level i s input to ____ rst, and the program is executed from the eit vector entry o f the reset interrupt. all internal resources including the intern al pll (4x clock generator) are initialized. in order to stabilize pll oscillation, ____ the "l" input to rst should last a minimum of 2 ms after vcc stabi- lizes to the specified voltage level. single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 29 clock generating circuit the M32000D3FP has a clock multiplier circuit and operates a t four times the input frequency. the internal operation frequency becomes 66.6 mhz when a 16.65 mhz clock is input to clkin. a capacit or (c) should be connected to the pllcap pin, and the clock is inpu t to the clkin pin. the pllvcc and pllvss pins should be connected to the power source or the ground, respectively. addressing mode m32r family supports the following addressing modes. < register direct > the general-purpose register or the control register to be p rocessed is specified. < register indirect > the contents of the register specify the address in memory t o be accessed. this mode can be used by all load/store instructio ns. < register relative indirect > (the contents of the register) + (16-bit immediate value whi ch is sign- extended to 32 bits) specify the address in memory to be acc essed. < register indirect and register update > ? 4 is added to the register contents (the contents of the register before update specify the address in memory to be accessed [ ld instruction] ? 4 is added to the register contents (the contents of the register after update specify the address in memory to be accessed) [ st instruction] ? 4 is subtracted from the register contents (the contents of the register after update specify the address in memory to be accessed) [ st instruction] < immediate > the 4-, 5-, 8-, 16- or 24-bit immediate value. < pc relative > (the contents of pc) + (8, 16, or 24-bit displacement which is sign- extended to 32 bits and 2 bits left-shifted) specify the add ress in memory to be accessed. fig. 32 oscillation circuit M32000D3FP 18 (clkin) 16 (pllcap) 15 (pllvss) c 14 (pllvcc) vcc pll clock generating circuit clock input recommended values in circuit c : 1000 pf single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 30 instruction set a total of 83 instructions are implemented. single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 31 single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 32 power source voltage input voltage output voltage power consumption operating temperature storage temperature absolute maximum ratings ratings topr = 25 c conditions parameter vcc vi vo pd topr tstg symbol unit v v v mw c c min. max. C0.5 C0.5 C0.5 0 C65 4.6 4.6 4.6 1000 70 150 recommended operating conditions (vcc = 3.3 v 0.3 v, topr = 0 to 70 c unless otherwise noted) vcc vih vil ioh (see note) iol (see note) cl ratings max. 3.6 vcc+0.3 vcc+0.3 0.8 0.2vcc 2 2 50 v v v v v ma ma pf symbol parameter unit min. 3.0 2.0 0.8vcc C0.3 C0.3 power source voltage h input voltage all inputs except following ____ rst pin l input voltage all inputs except following ____ rst pin h output current l output current output load capacity typ. note : ioh and iol represent the maximum values of dc current loa d. intermittent current that is generated during output need not to be considered as long as the output load capacity is within the specified range. single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 33 ioh = C2 ma iol = 2 ma vo = 0 to vcc vih = 0 to vcc +0.3 v vih = 0 to vcc +0.3 v average in normal operation mode vcc = 3.3 v average in cpu sleep mode vcc = 3.3 v average in standby mode vcc = 3.3 v all pins h output voltage l output voltage output current in off state h input current l input current power source current pin capacitance voh vol ioz iih iil icc c dc characteristics electrical characteristics (vcc = 3.3 v 0.3 v, topr = 0 to 70 c unless otherwise noted) ratings max. 0.4 10.0 10.0 C10.0 200 150 1500 15 v v a a a ma ma a pf symbol parameter unit min. 2.4 C10.0 test conditions typ. 120 80 single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 34 min. max. 5 2 5 2 ac characteristics timing requirements (vcc = 3.3 0.3 v, cl = 50 pf, topr = 0 to 70 c unless oth erwise noted) limits symbol parameter min. input rise transition time input fall transition time test conditions cmos input ____ rst pin cmos input ____ rst pin ( 1) input transition time tr(input) tf(input) unit ns ms ns ms reference number 1 2 limits symbol parameter clock input cycle time external clock input h pulse width external clock input l pulse width external clock input rising time external clock input falling time reset input l pulse width wakeup input l pulse width ( 2) clock, reset and wakeup timing tc(clkin) tw(clkinh) tw(clkinl) tr(clkin) tf(clkin) tw(rst) tw(wkup) max. 100 5 5 unit ns ns ns ns ns ms ms reference number 60 1/4clkin 1/4clkin 2 2 5 6 7 8 9 10 11 limits symbol parameter min. data input set-up time before clkin data input hold time after clkin __ dc input h set-up time before clkin __ dc input h hold time after clkin __ dc input l set-up time before clkin __ dc input l hold time after clkin test conditions ( 3) read and write timing max. unit ns ns ns ns ns ns reference number 5 2 10 2 10 2 30 31 36 37 38 39 tsu(d-clkin) th(clkin-d) tsu(dch-clkin) th(clkin-dch) tsu(dcl-clkin) th(clkin-dcl) test conditions single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 35 ( 4) arbitration and external bus master read/write timing limits symbol min. test conditions max. unit ns ns ns ns ns ns ns ns 5 2 10 2 5 3 5 3 40 41 48 49 50 51 52 53 tsu(hreq-clkin) th(clkin-hreq) tsu(cs-clkin) th(clkin-cs) tsu(a-clkin) th(clkin-a) tsu(d-clkinl) th(clkinl-d) parameter _____ hreq input set-up time before clkin _____ hreq input hold time after clkin __ cs input set-up time before clkin __ cs input hold time after clkin address input set-up time before clkin address input hold time after clkin data input set-up time before clkin data input hold time after clkin limits symbol parameter min. ___ int input pulse width (see note) ___ sbi input pulse width (see note) test conditions ( 5) interrupt control unit timing tw(int) tw(sbi) max. unit ns ns reference number tc(clkin) tc(clkin) 63 64 ___ ___ note: both int and sbi are level-sense inputs. keep them at an " l" level until the interrupt is accepted. ( 6) i/o port timing limits symbol parameter min. port input l pulse width port input h pulse width test conditions tw(portinl) tw(portinh) max. unit ns ns reference number 30 30 69 70 reference number single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 36 switching characteristics (vcc = 3.3 0.3 v, cl = 50 pf, topr = 0 to 70 c unless oth erwise noted) limits symbol parameter test conditions ( 1) output transition time tr(output) tf(output) reference number 3 4 min. unit max. 8 8 typ. output rising transition time output falling transition time ns ns ( 2) read and write timing limits symbol td(clkin-bshx) td(clkin-bsl) td(clkin-bslx) td(clkin-bsh) td(clkin-av) td(clkin-ax) td(clkin-bcv) td(clkin-bcx) td(clkin-sidv) td(clkin-sidx) td(clkin-stv) td(clkin-stx) td(clkin-rwv) td(clkin-rwx) td(clkin-bursthx) td(clkin-burstl) td(clkin-burstlx) td(clkin-bursth) td(clkin-dzx) td(clkin-dv) td(clkin-dvx) td(clkin-dxz) reference number 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 32 33 34 35 min. unit max. __ bs = h effective time after clkin __ bs = l delay time after clkin __ bs = l effective time after clkin __ bs = h delay time after clkin address delay time after clkin address effective time after clkin ____ ___ bch, bcl delay time after clkin ____ ___ bch, bcl effective time after clkin sid delay time after clkin sid effective time after clkin st delay time after clkin st effective time after clkin __ r/w delay time after clkin __ r/w effective time after clkin ______ burst = h effective time after clkin ______ burst = l delay time after clkin ______ burst = l effective time after clkin ______ burst = h delay time after clkin data output enable time after clkin data output delay time after clkin data output effective time after clkin data output disable time after clkin parameter ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 12 tc(clkin)/4+8 16 16 16 16 16 12 12 18 16 test conditions 0 tc(clkin)/4 0 0 0 0 0 0 0 0 0 single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 37 ( 3) arbitration and external bus master read/write timing limits symbol test conditions td(clkin-hackhx) td(clkin-hackl) td(clkin-hacklx) td(clkin-hackh) td(clkin-az) td(clkin-azx) td(clkin-dzx) td(clkin-dv) td(clkin-dxz) td(clkin-dvx) td(cs-dczx) td(clkin-dchx) td(clkin-dcl) td(clkin-dcxz) td(clkin-dclx) 42 43 44 45 46 47 54 55 56 57 58 59 60 61 62 max. _____ hack = h effective time after clkin _____ hack = l delay time after clkin _____ hack = l effective time after clkin _____ hack = h delay time after clkin address output disable time after clkin address output enable time after clkin data output enable time after clkin data output delay time after clkin data output disable time after clkin data output effective time after clkin __ __ dc output enable time after cs __ dc = h effective time after clkin __ dc = l delay time after clkin __ dc output disable time after clkin __ dc = l effective time after clkin parameter 12 12 16 18 16 16 16 min. 0 0 0 0 0 0 0 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns unit reference number ( 4) standby timing limits symbol test conditions td(clkin-stbyhx) td(clkin-stbyl) td(clkin-stbylx) td(clkin-stbyh) reference number 65 66 67 68 min. unit max. parameter ns ns ns ns tc(clkin)n/4+15 tc(clkin)n/4+15 _____ stby = h effective time after clkin _____ stby = l delay time after clkin (see note) _____ stby = l effective time after clkin _____ stby = h delay time after clkin (see note) 0 0 _____ note: the stby signal is synchronized with the internal clock, therefore i ts timing changes at 0, 90, 180 and 270 (n=0, 1, 2, 3) de gree phase of clkin. limits symbol parameter min. port output l pulse width (see note) port output h pulse width (see note) test conditions ( 5) i/o port timing tw(portoutl) tw(portouth) max. unit ns ns reference number 12 12 71 72 note: the minimum pulse width value is that where the output is c hanged within 1 clock of the internal clock. software proces sing ti me to write to the port data register is not included. single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 38 fig. 34 output switching characteristic measurement circuit c l = 50 pf cmos output cmos output ( during floating delay time measurement) measured pin c l = 50 pf measured pin 0.5v cc 1.0 k w fig. 35 input waveform and timing reference point during ch aracteristic measurement fig. 36 output timing measurement point during characterist ic measurement timing reference point 0.8 vcc 0.2vcc cmos output (when not specified) 0.9vcc cmos output (during floating delay time measurement) 0.1vcc 0.6vcc 0.4vcc "h" ? "z" "l" ? "z" "z" ? "h" "z" ? "l" timing reference point (when not specified) "h" input level "l" input level vcc 0.0 v 0.9 vcc 0.1vcc 0.8vcc 0.9vcc 0.1vcc 0.2vcc cmos input schmitt trigger input "h" input level "l" input level vcc 0.0 v clkin input "h" input level "l" input level single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 39 cmos input (except for schmitt trigger input and clkin input) schmitt trigger input (rst) 0.8 vcc 0.9vcc 0.1vcc 0.2vcc t r(input) t f(input) t r(input) t f(input) 1 1 2 2 output pin 0.8vcc 0.2vcc t r(output) t f(output) 3 4 fig. 37 input transition time fig. 38 output transition time fig. 39 clock reset and wakeup timing t w(rst) rst 0.5vcc 0.8vcc 0.2vcc t w(clkinh) t w(clkinl) t r(clkin) t f(clkin) clkin (input) (input) t c(clkin) 5 6 7 8 9 10 t w(wkup) wkup (input) 11 *1 the wkup and rst signals can be input asynchronously. when returning from standby mode, the same timing applie s. *1 *1 single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 40 clkin (input) (output) (output) 0.5 vcc (input) (output) d0 to d15 d0 to d15 (input) t d(clkin-dv) t d(clkin-dzx) t d(clkin-dvx) t d(clkin-dxz) t su(dcl-clkin) t h(clkin-dcl) t su(d-clkin) t h(clkin-d) bs bch, bcl dc 13 15 30 31 32 33 34 35 38 39 (output) a8 to a30 t d(clkin-av) 16 (output) t d(clkin-stv) sid, st 22 (output) t d(clkin-rwv) r/w 24 (output) burst t d(clkin-bsh) t d(clkin-burstl) 27 t d(clkin-bursth) 29 t d(clkin-bsl) t d(clkin-bcv) 18 t d(clkin-sidv) 20 12 t d(clkin-bshx) 14 t d(clkin-bslx) t d(clkin-ax) 17 t d(clkin-bcx) 19 t d(clkin-stx) 23 t d(clkin-sidx) 21 t d(clkin-rwx) 25 t d(clkin-bursthx) 26 t d(clkin-burstlx) 28 t su(dch-clkin) t h(clkin-dch) 36 37 *1 the set up/hold of dc = "h" may vary depending on the wai t cycle insertion or when an idle cycle occurs. *1 *1 *2 all switching characteristics and timing requirements bas ed on the falling edge of clkin are calculated according to the internal clkin (duty ratio is 50%) . when designing external peripheral circuits, the correction for the duty cy cle of the actual clkin is necessary. ? minimum value of td(clkin-bslx) = (value in table) C (corr ection value) = 15 C (60 x 5/100) = 12 [ns] ? maximum value of td(clkin-bsh) = (value in table) + (corre ction value) = (60/4 + 8) + (60 x 5/100) = 26 [ns] *2 *2 *2 *2 *2 *2 [example] bs signal transition ("l" C> "h") when inputting 16.65 mhz clock whose duty ratio is 45 - 55% ( 5%) to clkin: 0.5 vcc fig. 40 read/write timing single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 41 fig. 41 bus arbitration timing clkin hreq hack a8 to a30, sid, st, bs, bch, bcl, r/w, burst (output) (input) (input) (output) *1 the hreq signal can be input asynchronously. *2 all switching characteristics and timing requirements bas ed on the falling edge of clkin are calculated according to the internal clkin (duty ratio is 50%) . when designing external peripheral circuits, the correction for the duty cy cle of the actual clkin is necessary. ? minimum value of td(clkin-hackhx) = (value in table) C (co rrection value) = 0 C (60 x 5/100) = C3 [ns] ? maximum value of td(clkin-hackl) = (value in table) + (cor rection value) = 12 + (60 x 5/100) = 15 [ns] [example] hack signal transition ("h" C> "l") when inputting 16.65 mhz clock whose duty ratio is 45 - 55% ( 5%) to clkin: 0.5vcc 0.5vcc t d(clkin-hackl) t d(clkin-hackhx) t d(clkin-hackh) t d(clkin-hacklx) t d(clkin-azx) t d(clkin-az) t su(hreq-clkin) 41 42 43 44 45 46 47 *1 *1 t h(clkin-hreq) 40 *2 *2 *2 *2 single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D3FP 42 fig. 42 external bus master read/write timing clkin (input) (input) 0.5 vcc (input) (output) d0 to d15 d0 to d15 (input) t h(clkinl-d) hreq r/w 40 52 53 54 55 (output) t su(hreq-clkin) hack 41 43 t d(clkin-hackl) 45 (input) cs 48 t su(cs-clkin) 49 t h(clkin-cs) t d(clkin-dv) t d(clkin-dzx) 50 t su(a-clkin) 51 t h(clkin-a) (output) dc 60 t d(clkin-dcl) 59 t d(clkin-dchx) 42 t d(clkin-hackhx) 44 58 t d(cs-dczx) t d(clkin-hackh) t d(clkin-hacklx) t h(clkin-hreq) 50 51 (input) a8 to a30 bch, bcl 50 51 50 51 48 49 t su(d-clkinl) 48 49 t d(clkin-dxz) t d(clkin-dvx) 56 57 t d(clkin-dclx) t d(clkin-dcxz) 58 60 59 62 61 62 61 *1 all switching characteristics and timing requirements based on the falling edge of clkin are calculated according to the internal clkin (duty ratio is 50%) . when designing external peripheral circuits, the correction for the duty cycle of the actual clkin is necessary. ?minimum value of tsu(cs-clkin) = (value in table) + (correction value) = 10 + (60 x 5/100) = 13 [ns] ?minimum value of th(clkin-cs) = (value in table) + (correction value) = 2 + (60 x 5/100) = 5 [ns] *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 [example] cs signal transition ("l" ? "h") when inputting 16.65 mhz clock whose duty ratio is 45 - 55% ( 5%) to clkin: single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP 43 *2 the stby goes to an "l" level when switched to the standb y mode. *3 when returning from standby mode, the stby signal goes to an "h" level 1 clkin after sampling that wkup has returned from "l" to "h", or 3 c lkins after sampling that rst = "l". t d(clkin-stbyl) stby (output) 66 clkin (input) t d(clkin-stbyh) 68 *1 *2 *1 *3 degree phase of clkin. t d(clkin-stbyhx) 65 t d(clkin-stbylx) 67 internal clock (66.6 mhz) *1 the stby signal is synchronized with the internal clock therefore, its timing changes at 0, 90, 180 and 270 fig. 43 interrupt input timing fig. 44 standby timing px t w(portinl) t w(portinh) 69 70 [for input] px t w(portoutl) t w(portouth) 71 72 [for output] fig. 45 i/o port timing int sbi (input) (input) t w(int) t w(sbi) *1 63 64 *1 *1 the int and sbi signals can be input asynchronously. when returning from cpu sleep mode, the same timing applies. this timing value is "a value necessary for sampling the inp ut to pins", however, not "a value that guarantees the interrupt acceptance". the interrupt request is a level-sensed input , and should b e kept "l" until it is accepted. notes regarding these materials ? these materials are intended as a reference to assist our cu stomers in the selection of the mitsubishi semiconductor pro duct b est suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. ? mitsubishi electric corporation assumes no responsibility fo r any damage, or infringement of any third-partys rights, o rigina ting in the use of any product data, diagrams, charts or cir cuit application examples contained in these materials. ? all information contained in these materials, including prod uct data, diagrams and charts, represent information on prod ucts a t the time of publication of these materials, and are subjec t to change by mitsubishi electric corporation without notice due to product improveme nts or other reasons. it is therefore recommended that custo mers co ntact mitsubishi electric corporation or an authorized mitsu bishi semiconductor product distributor for the latest product information befor e purchasing a product listed herein. ? mitsubishi electric corporation semiconductors are not desig ned or manufactured for use in a device or system that is us ed und er circumstances in which human life is potentially at stake . please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use o f a pro duct contained herein for any specific purposes, such as app aratus or systems for transportation, vehicular, medical, aerospace, nuclear, or u ndersea repeater use. ? the prior written approval of mitsubishi electric corporatio n is necessary to reprint or reproduce in whole or in part t hese m aterials. ? if these products or technologies are subject to the japanes e export control restrictions, they must be exported under a licen se from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control law s and regulations of japan and/or the country of destination is pro hibited. ? please contact mitsubishi electric corporation or an authori zed mitsubishi semiconductor product distributor for further detai ls on these materials or the products contained therein. keep safety first in your circuit designs! ? mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when m aking y our circuit designs, with appropriate measures such as (i) p lacement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mish ap. ? 1998 mitsubishi electric corp. revised edition, effective may. 1998. specifications subject to change without notice. single-chip 32-bit cmos micr ocomputer mitsubishi microcomputers M32000D3FP rev. rev. no. date 1.0 first edition 970507 2.0 __ ? dc signal explanation revised (page 19). 970901 ? figures 17 to 25 revised (page 21 to page 25). ? 2 to 7 clkin clock periods are ~ ? 3 to 7 clkin clock periods are ~ (left column in page 24) ? 2 to 7 clkin clock periods are ~ ? 3 to 7 clkin clock periods are ~ (left column in page 25) ? dc characteristics, ac characteristics, and switching cha racteristics revised (page 33 to 37). ? figures 40 to 43 revised (page 40 to 43). 2.1 __ ? "after dc outputs an ~ clkin falling edge." revised (line 14, page 24). 980501 ? notes in figure 23 revised (page 24). __ __ __ ? "after dc outputs an ~ clkin falling edge." revised (line 15, page 25). ? notes in figure 24 revised (page 25). ? table 2 revised (page 28). ? (3) arbitration and external bus master read/write timing symbol parameter ~~ ~ td(cs-dczx) dc output enable time after cs co rrected (page 37). ?" 58 td(cs-dczx) *1 " in fig. 42 corrected (page 42). ? notes in figure 44 revised (page 43). revision description list M32000D3FP data sheet (1/1) revision description |
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